Cache Awareness in Blocking Techniques

To date, data locality optimizing algorithms mostly aim at providing strategies for blocking and reordering loops. But little research has been devoted to the nal step: nding the optimal block size, i.e., a block size that provides the best possible performance. Optimal block sizes are currently computed as if a cache is a local memory, i.e., cache interferences are ignored. Case-studies have already shown that cache interferences can greatly aaect the optimal block size value. The purpose of this article is to show that analytical modeling of cache interferences can be used to compute near-optimal block sizes for blocked loop nests. First, the method for evaluating cache interferences is presented. Second, the model is validated by correlating the estimated miss ratio with the simulated miss ratio and the execution time of various loop nests. Then, current techniques for computing the optimal block size are analytically and experimentally shown to yield below-optimal performance. Finally, current block size computation techniques are augmented with analytical modeling of cache interferences and TLB misses, and this new technique is shown to yield near-optimal performance and make blocking techniques safe. Reciprocally, it is also shown that even when no capacity miss occurs, nely tuned blocking techniques can be used to signiicantly reduce the number of cache interferences.